ASIC Design of a Hybrid Pipelined-Parallel Digital Fuzzy Processor

Fuzzy processors are commonly used in different control systems. They make use of fuzzy logic while conventional processors rely on classical crisp logic. Classical logic needs accurate equations and precise data to function properly. On the other hand, fuzzy logic is a precise logic that has been created to capture the approximate, inexact nature of the real world. Fuzzy logic is a form of many-valued logic and holds truth values between 0 and 1. It aims to represent the model of human reasoning that is needed to make decisions in an environment where information is partially true, incomplete, conflicting and imprecise. Fuzzy processors are recommended for complex and non-linear processes which are difficult for conventional processors to control due to the lack of simple mathematical models. This thesis presents the ASIC design of a digital fuzzy processor using UMC 0.18 um Logic GII process. The proposed processor can work on arbitrary membership functions, resulting in higher accuracy as compared to triangular or trapezoidal functions. Separate storage of the sets of antecedents common to groups of fuzzy rules, leads to reduction in computation time. Pipelining and parallelism in the architecture speed up the computation. The architecture has three pipe stages and can operate on eight inputs in parallel. The processor works at a clock frequency of 100 MHz. For a system of 256 active rules, the processor produces results at an interval of 4.5 us and consumes 85 mW from a 1.8 V supply. The ASIC has lesser computation time and consumes lower power compared to state of the art RISC and CISC architecture processors.